1. Field Of The Invention
The present invention relates to a solid imaging device which provides high sensitivity.
2. Description Of The Related Art
CMOS type image sensors, i.e., image sensors formed through a CMOS process, have been proposed. CMOS type image sensors are classified into: PPS (passive pixel sensors) for reading a signal charge which has been generated through photoelectric conversion in each pixel without alteration to the signal charge; and APS (active pixel sensors) for reading such a signal charge after having been amplified, the amplification occurring on a pixel-to-pixel basis. Both types of CMOS image sensors usually employ a photodiode (constituting a p-n junction) as a photoelectric conversion section.
In a PPS type CMOS image sensor, as shown in FIG. 9, a signal charge from a photodiode 5 is switched via a single MOS transistor 3, which is located within the same pixel, so as to be read onto a signal line 13 without being amplified. A signal for causing the switching of the MOS transistor 3 is supplied via a pixel selection clock line 11.
FIG. 10A shows a plan view of an actual pattern corresponding to the circuit diagram shown in FIG. 9. FIG. 10B shows a cross-sectional view taken along line Axe2x80x94A of FIG. 10A. FIG. 10C shows a cross-sectional view taken along line Bxe2x80x94B of FIG. 10A. In FIG. 10A, the elements which correspond to any circuit elements shown in FIG. 9 (e.g., the photodiode 5) are indicated by the same reference numerals as used therein.
As seen from FIGS. 10B and 10C, the photodiode 5 for performing photoelectric conversion is constructed from an n+ layer 130 formed on a p well 110, which in turn is formed on a pxe2x88x92 semiconductor substrate 100. A p-n junction is formed at an interface between the n+ layer 130 and the p well 110, where photoelectric conversion takes place. The n+ layer 130 is divided into a portion 130a (the hatched portion in FIG. 10A) which substantially functions as a photosensitive portion (i.e., a photodiode) and a portion 130b which substantially functions as a source/drain of the MOS transistor 3. These portions 130a and 130b are usually formed in an integral manner. In the step of forming the n+ layer 130 composing the photodiode 5, an n+ layer 131 (which later becomes the source/drain of the MOS transistor 3) is formed, usually concurrently, on the p well 110 so as to be located-at a predetermined distance from the n+ layer 130. As a result, a channel 3a of the MOS transistor 3 is formed in the p well 110. By disposing the pixel selection clock line 11 above the channel 3a with an insulation layer (e.g., an oxidation film; not shown) interposed therebetween, and applying a predetermined voltage thereto, a switching operation of the MOS transistor 3 occurs. Thus, the MOS transistor 3 is activated or turned on so that a signal (charge) from the photodiode 5 is transmitted, via a contact formed in the source/drain n+ layer 131, to a signal line 13 (not shown in FIG. 10A) which is formed so as to intersect the clock line 11.
On the other hand, an APS type CMOS image sensor requires a photoelectric conversion section, an amplification section, a pixel selection section, and a reset section to be formed in association with each pixel. Usually, three to four MOS transistors (T) are employed in addition to a photodiode (PD). FIG. 11 shows an exemplary structure of a portion of an APS type CMOS image sensor corresponding to two pixels, where three transistors (T) and one photodiode (PD) are incorporated (Mabuchi et al., xe2x80x9cA xc2xc INCH 330K PIXEL VGA CMOS IMAGE SENSORxe2x80x9d, a technical report of the Institute of Image Information and Television Engineers, IPU97-13, March 1997xe2x80x9d). As shown in FIG. 11, a photodiode 5, an amplification section 1. a reset section 2, a pixel selection section 3; a pixel selection clock line 11, a reset clock line 12, a signal line 13, and a supply line 14 are provided for each pixel.
FIG. 12A shows a plan view of an actual pattern corresponding to the circuit diagram shown in FIG. 11. FIG. 12B shows across-sectional view taken along line Axe2x80x94A of FIG. 12A. FIG. 12C shows a cross-sectional view taken along line Bxe2x80x94B of FIG. 12A. In FIG. 12A, the elements which correspond to any circuit elements shown in FIG. 11 (e.g., the photodiode 5) are indicated by the same reference numerals as used therein. The photodiode 5 and three transistors 1 to 3 are formed so as to be aligned along the vertical direction in FIG. 12A.
As seen from FIGS. 12B and 12C, the photodiode 5 for performing photoelectric conversion is constructed from an n+ layer 130 formed on a p well 110, which in turn is formed on a pxe2x88x92 semiconductor substrate 100. A p-n junction is formed at an interface between the n+ layer 130 and the p well 110, where photoelectric conversion takes place. In the step of forming the n+ layer 130 composing the photodiode 5, n+ layers 131 (which later become the respective source/drains of the MOS transistors 1 to 3) are formed, usually concurrently, on the p well 110 so as to be positioned at predetermined distances from the n+ layer 130.
In FIGS. 9 to 12A, 12B, and 12C, the transistors 1, 2, and 3 are all n type MOS transistors, and the photodiode 5 is a p-n junction type diode. Such elements can be easily formed by using a standard CMOS process.
Now, the operation principles of a photodiode will be briefly discussed with reference to FIGS. 13A and 13B. Light which enters a p-n junction of a photodiode will be subjected to photoelectric conversion before it reaches an ingression depth Lp (on average), thereby generating electron/hole pairs. FIG. 13B shows the light intensity of the incident light against the depth as taken from the substrate surface. The amount of electrons which are effectively stored in the n surface layer as a signal charge is defined as a sum of the following three components:
(i) all of the electrons that have been generated in a depletion layer which is formed at the p-n junction interface;
(ii) a number of electrons equivalent to the number of the holes generated in a neutral region of the n layer that have reached, through diffusion, the end of the depletion layer formed at the junction interface; and
(iii) a number of electrons generated in a neutral region of the p layer that have reached, through diffusion, the end of the depletion layer formed at the junction interface.
Therefore, enhancement of sensitivity can be most efficiently achieved by expanding the area of the depletion layer (component (i)). Component (ii) increases as the diffusion length of the holes within the n layer becomes larger than the n layer junction depth Xj (FIG. 13A). Component (iii) increases as the diffusion length of the electrons within the p layer increases. However, an increase in the diffusion length of the electrons in the p layer results in more eminent crosstalk occurring between adjoining pixels, resulting in problems such as decrease in the resolution and/or a flare phenomenon (i.e., influence of irradiation of intense light on other regions).
In the structures illustrated in FIGS. 9; 10A to 10C; 11; and 12A to 12C, the photodiode 5 is formed on the CMOS-process-based p well 110. In particular, in the APS type CMOS image sensor shown in FIGS. 11 and 12A to 12C, the area occupied by the transistors 1 to 3 must be minimized in order to secure a large photodiode area. Reducing the transistor dimensions requires increasing the p type impurity concentration in the p well 110. However, as shown in FIG. 13A, an increased p type impurity concentration in the p well 110 results in a decrease in the thickness Xdep of the depletion layer formed at the p-n junction interface.
In the following discussion, silicon is exemplified as a semiconductor substrate material.
In a common CMOS process, a p well concentration Np of about 1xc3x971017cmxe2x88x923 is used. Therefore, under the condition that the bias voltage Vb=3 V, the thickness of the depletion layer Xdep will be about 0.23 xcexcm. The most recent CMOS process technique can reduce the junction depth Xj down to about 0.15 xcexcm. In the case of about 550 nm, which is the wavelength within the visible spectrum that is best perceived by the human eye, the ingression depth Lp is about 1.5 xcexcm. In other words, the depletion layer, which provides for the most efficient photoelectric conversion, only accounts for about 15% of the effective photoelectric conversion region, and the surface n+ layer only accounts for about 10%. Therefore, a major portion of the effective photoelectric conversion region exists in the p well and the underlying p substrate region. This results in a decrease in sensitivity (in the case where the diffusion length of electrons within the p well is small) or a decrease in resolution and/or a flare phenomenon (in the case where the diffusion length of electrons within the p well is large).
FIG. 14 shows a conventional technique disclosed in Japanese Laid-open Publication No. 9-232555 for solving the aforementioned problems of the prior art techniques. The circuit shown in FIG. 14 is substantially the same as that shown in FIG. 11. For conciseness, like numerals are used for like elements. One feature of the circuit shown in FIG. 14 is the structure of the photodiode 5: specifically, a photoelectric conversion section (photosensitive portion) is formed on the n substrate 200. As a result, the signal charge (electrons) which has been generated in a portion deep into the semiconductor is discharged toward the n substrate 200, thereby greatly reducing the crosstalk between pixels. In addition, an n layer 220, having a lower concentration than that of an n+ surface layer 230, is provided between the n+ surface layer 230 and a p well 210 (which together form an n-p junction for photoelectric conversion), thereby reducing the n-p junction capacitance and increasing the detection sensitivity (i.e., the charge voltage conversion gain).
However, the aforementioned technique has the following problems: First, providing a p well on an n substrate and further providing an n transistor and an n-p junction photodiode therein leads to increased susceptibility to a longitudinal n-p-n bipolar action. In the photosensitive region, in particular, it is difficult to provide a contact from the substrate surface to a p well which is situated at an intermediate depth, because doing so will require extra wiring, which contradicts the order of securing a sufficiently large photodiode area. Therefore, the p well potential (e.g., the ground potential) may not be sufficiently fixed. This results in increased susceptibility to a longitudinal n-p-n bipolar action as well as malfunctioning.
Furthermore, in order to reduce the n-p junction capacitance of the photodiode, it is desirable that the concentration of the n layer 220 (which is interposed between the n+ surface layer 230 and the p well 210) be equal to or smaller than the concentration of the p well 210. For example, under the conditions that n+ layer concentration Ns=1xc3x971021cmxe2x88x923; p well concentration Np=1xc3x971017cmxe2x88x923; and bias voltage Vb=3 V, the n-p junction capacity Cj can be calculated as follows:
Cj=46 nF/cm2 (if the n layer 220 is entirely omitted);
Cj=44 nF/cm2 (if Nn=1xc3x971018cmxe2x88x923);
Cj=33 nF/cm2 (if Nn=1xc3x971017cmxe2x88x923); and
Cj=14 nF/cm2 (if Nn=1xc3x971016cmxe2x88x923).
Herein, it is assumed that the n layer 220 has a concentration Nn. As seen from the above calculation, a significant effect of reducing the junction capacitance emerges as the concentration Nn becomes sufficiently smaller than the concentration Np.
However, it is very difficult to form the n layer 220 so as to have a concentration Nn which is equal to or smaller than the p well concentration Np. Specifically, forming the n layer 220 by employing a single additional ion implantation step as disclosed in Japanese Laid-open Publication No. 9-232555 requires the concentrations of the respective layers to be selected in accordance with the intensity profiles shown in FIG. 15 (in which the concentration profiles of the respective layers are denoted by the same numerals as used in FIG. 14). Forming the n layer 220 with a concentration which is equal to or lower than that of the p well 210 requires implanting an n type impurity 220xe2x80x2 at a slightly higher concentration than that of the p well 210 (for example, forming the n layer 220 with a concentration which is {fraction (1/10)} times the concentration of the p well 210 requires implantation of an n type impurity 220xe2x80x2 at a concentration which is 1.1 times that of the p well 210). In practice, however, substantial technical difficulties exist in achieving an n type impurity implantation at precisely 1.1 times that of the p well 210.
A solid imaging device according to the present invention includes: a semiconductor substrate of a first conductivity type; a layer of a second conductivity type formed on a surface of the semiconductor substrate, the layer at least including a photosensitive portion of the second conductivity type; and a MOS transistor of the second conductivity type coupled to the photosensitive portion, wherein the solid imaging device further includes a layer of the first conductivity type in at least a channel region of the MOS transistor of the second conductivity type, the layer of the first conductivity type having an impurity concentration which is higher than an impurity concentration of the semiconductor substrate, and wherein at least a portion of a boundary of the layer of the second conductivity type is in direct contact with the semiconductor substrate.
In one embodiment of the invention, at least a portion of the photosensitive portion of the second conductivity type is in contact with the semiconductor substrate.
In another embodiment of the invention, the layer of the second conductivity type further includes a further layer of the second conductivity type between the photosensitive portion of the second conductivity type and the semiconductor substrate, the further layer of the second conductivity type having an impurity concentration which is lower than an impurity concentration of the photosensitive portion, at least a portion of the further layer of the second conductivity type being in contact with the semiconductor substrate.
In still another embodiment of the invention, the impurity concentration of the layer of the first conductivity type is at least about ten times higher than the impurity concentration of the semiconductor substrate.
In still another embodiment of the invention, the impurity concentration of the further layer of the second conductivity type is at least about ten times higher than the impurity concentration of the semiconductor substrate.
In still another embodiment of the invention, the further layer of the second conductivity type is in contact with the layer of the first conductivity type, a boundary between the further layer of the second conductivity type and the layer of the first conductivity type being located outside the photosensitive portion.
In still another embodiment of the invention, the solid imaging device includes a plurality of said photosensitive portions and said further layers of the second conductivity type associated therewith, wherein one of the plurality of said further layers of the second conductivity type associated with one of the plurality of said photosensitive portions is formed independently from another of the plurality of said further layers of the second conductivity type.
In still another embodiment of the invention, the MOS transistor of the second conductivity type is operable to retain a level of a signal from the photosensitive portion.
In still another embodiment of the invention, the solid imaging device further includes one or more further MOS transistors of the second conductivity type associated with the photosensitive portion of the second conductivity type, wherein the MOS transistor of the second conductivity type and the further one or more MOS transistors of the second conductivity type are operable to amplify a level of a signal from the photosensitive portion.
In still another embodiment of the invention, the photosensitive portion of the second conductivity type is formed of the same material as that of a source/drain of the MOS transistor of the second conductivity type.
In still another embodiment of the invention, the photosensitive portion of the second conductivity type is formed of a material different from that of a source/drain of the MOS transistor of the second conductivity type.
In another aspect of the invention, there is provided a method for producing the aforementioned solid imaging device, wherein the solid imaging device further includes CMOS circuitry for controlling a signal from the photosensitive portion, the CMOS circuitry including: a well of the first conductivity type and a well of the second conductivity type, the wells being formed on the semiconductor substrate of the first conductivity type; a MOS transistor of the second conductivity type formed on the well of the first conductivity type; and a MOS transistor of the first conductivity type formed on the well of the second conductivity type, the method including a step of forming the layer of the first conductivity type and the well of the first conductivity type on a surface of the semiconductor substrate through a simultaneous layer formation process.
In yet another aspect of the invention, there is provided a method for producing the aforementioned solid imaging device, wherein the solid imaging device further includes CMOS circuitry for controlling a signal from the photosensitive portion, the CMOS circuitry including: a well of the first conductivity type and a well of the second conductivity type, the wells being formed on the semiconductor substrate of the first conductivity type; a MOS transistor of the second conductivity type formed on the well of the first conductivity type; and a MOS transistor of the first conductivity type formed on the well of the second conductivity type, the method including the steps of: forming the layer of the first conductivity type and the well of the first conductivity type on a surface of the semiconductor substrate through a simultaneous layer formation process; and forming the further layer of the second conductivity type and the well of the second conductivity type on the surface of the in semiconductor substrate through a simultaneous layer formation process.
Thus, the invention described herein makes possible the advantage of: providing a highly-sensitive and high-solution CMOS type solid imaging device having a photodiode section which attains a low flare level with a low dark current, without introducing a longitudinal bipolar structure in a photosensitive portion, and without the need to employ any special ion implantation step in addition to a usual CMOS process.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.